Emulation of SEU Effect In Bitstream of FPGA
نویسنده
چکیده
This work analyzes an effect of single-bit error in configuration memory of FPGA. Several fault models are proposed and described in detail. Software estimation of vulnerable bits from bitstream is presented, in conjunction with the SEU hardware emulator, which experimentally tests a correctness of the estimation. Results of several combinational benchmark are presented and s1488 benchmark discussed in detail.
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